1. Field of the Invention
This invention relates to data processing systems. More particularly, this invention relates to the testing of memory access signal connections between a data processing circuit and a memory coupled to that data processing circuit.
2. Description of the Prior Art
It is known to provide testing mechanisms for testing integrated circuits when they have been manufactured to ensure that they operate correctly. One known technique is to include serial scan chains into which test patterns, such as automatically generated test patterns (AGTPs), may be scanned in and result values scanned out to verify correct operation of the manufactured integrated circuits. As integrated circuits increase in complexity and have an increasing number of functional units embedded therein, the need for test in this way increases and the difficulty of gaining access to deeply embedded portions of the integrated circuit with no direct connection to the external pins of the integrated circuit also increases. These problems are further compounded in that different functional elements within the integrated circuit may be designed and produced by different suppliers who may not release full details of the design of their functional unit as this is proprietary information. This makes the design of appropriate test patterns to provide comprehensive test coverage more difficult.
In the above circumstances, one possibility is that the provider of the functional unit, such as a processor core, will also supply appropriate test patterns for testing that functional unit when it is integrated within a larger integrated circuit (system-on-chip) design. Whilst this approach works well in many cases, a difficulty arises when the particular functional unit may be connected to a variety of different forms of additional circuitry which necessitate different test patterns to be used. In this context, the functional unit provider can try to produce a suite of test patterns to cover all possible ways in which the functional unit may be used, but this is an onerous undertaking. As an example of this circumstance, a processor core may have a memory access port to which a memory of a variable size can be connected or optionally no memory at all connected. In order to test the memory access signal connections between the processor core and the memory, it would be possible to provide each of these signal connections with a scan chain cell such that test pattern data could be applied to and captured from these points. This would allow the connections to be tested without dependence upon the connected memory size. However, the memory access signal connections are often timing critical signal paths and the additional delay that may be introduced by inserting a multiplexer in these paths so as to accommodate a scan chain cell is a significant disadvantage. Furthermore, significant circuit area is consumed by scan chain cells and so it is desirable if possible to reduce these in number. It is known within test methodologies to control a data processing circuit with appropriately applied diagnostic signals such that it will exercise the memory access signal connections for a particular size of attached memory with the results of these stimulations being observed to ensure correct operation by checking the data fed back into the data processing circuit. However, such techniques are memory size specific and accordingly in order to deal with a variety of possible different memory sizes which may be attached, a disadvantageously large number of suitable test patterns need to be provided.